1. Field of the Invention
The present invention relates to a frequency synthesizer employing a phase synchronous loop, which is utilized in telecommunications systems such as TDMA (time-division multiple access) systems for satellite communications networks.
2. Description of the Prior Art
FIG. 1 is a block diagram showing one example of a known frequency synthesizer as disclosed in Japanese Laid-Open Patent Publication No. 61-134127. 10 is a voltage controlled oscillator (hereinafter called "VCO") for supplying an output signal having a frequency corresponding to a control voltage, at an output terminal 20. Numeral 12 is a variable frequency divider of a frequency division ratio variable type for providing frequency division of the output signal from VCO 10. Numeral 14 is a phase detector (PD) for comparing the phase of an output signal from the variable frequency divider 12 with the phase of a reference signal outputted from a reference signal generator 16. Numeral 18 indicates a loop filter for supplying, as a control voltage, a phase difference signal outputted from the phase detector 14 to the VCO 10 and for fixing the characteristic of the loop defined by the VCO 10, frequency divider 12, phase detector 14, and filter 18.
FIG. 2 is a circuit diagram showing one example of a structure of the loop filter 18. In the drawing, R.sub.1, R.sub.2 are resistors and C is a capacitor. Incidentally, R.sub.1 and R.sub.2 also represent the resistance values of the resistors and C indicates the capacitance value of the capacitor.
A description will now be made of the operation of the frequency synthesizer. The phase detector 14 serves to compare the phase of the output signal from the variable frequency divider 12 with the phase of the reference signal outputted from the reference signal generator 16 for producing therefrom a phase difference signal in the form of a mean voltage proportional to the resultant phase difference. The phase difference signal is used as the control voltage for the VCO 10 after having passed through the loop filter 18. This VCO 10 serves to generate an output signal having a frequency corresponding to the control voltage. Then, the output signal from VCO 10 is supplied to output terminal 20 and is frequency divided by the variable frequency divider 12. Given that the frequency division ratio set in the variable frequency divider 12 is N, the frequency of the output signal is equal to N times the frequency of the reference signal during a phase-locked period (steady state).
A filter often used as the loop filter 18 is the lag-lead type filter shown in FIG. 2. When the lag-lead type filter is adopted, the natural angular frequency .omega..sub.n of the loop and the damping coefficient .zeta. of the loop are expressed as follows: ##EQU1## where .tau..sub.1 =R.sub.1 C
.tau..sub.2 =R.sub.2 C PA1 K=loop gain of the loop PA1 K.sub..phi. =sensitivity (conversion gain) of the phase detector 14 PA1 N=frequency division ratio of the variable frequency divider 12
or ##EQU2## where K.sub.v =sensitivity (conversion gain) of the VCO 10
The frequency synthesizer produces different output frequencies whenever the frequency-division ratios N of the variable frequency divider 12 are changed over from one to another. However, the natural angular frequency and the damping coefficient are set such that the time interval or frequency changeover time that is required to make each of the output frequencies stable after a frequency changeover has been made by changing the frequency division ratio N of divider 12, becomes a value not exceeding a predetermined value over the entire range of possible output frequencies. In addition, the resistance values of R.sub.1, R.sub.2 and the capacitance value of C are determined by considering the operation of the loop filter 18 for eliminating noise or the like from the phase difference signal of detector 14 under steady state.
FIG. 3 is a circuit diagram showing an example of the loop filter 18 disclosed in the above-mentioned Japanese Laid-Open Patent Publication. In FIG. 3, 181-183 are switches for performing changeover between resistors R.sub.11, R.sub.12, R.sub.2 and resistors R.sub.11S =R.sub.11 .parallel.R.sub.115, R.sub.12S =R.sub.12 .parallel.R.sub.125 and R.sub.2S =R.sub.2 .parallel.R.sub.25. Numerals 184-186 are control terminals for receiving control signals used for the changeover of the switches 181-183. The resistance values of the respective resistors referred to above are established by the following inequalities, i.e., R.sub.11S &lt;R.sub.11, R.sub.12S &lt;R.sub.12, and R.sub.2S &lt;R.sub.2. Each of the switches 181-183 is left open in the steady state, and the loop filter 18 is comprised of the resistors R.sub.11, R.sub.12, R.sub.2 and the capacitor C. The switches 181-183 are closed by associated control signals when a frequency changeover is made, i.e. when the value of N is changed in the frequency divider 12. Since the resistance values of the resistors R.sub.11S, R.sub.12S, R.sub.2S are smaller than those of the resistors R.sub.11, R.sub.12, R.sub.2, and the loop filter 18 consists of the resistors R.sub.11S, R.sub.12S, R.sub.2S and the capacitor C when the switches are closed, two time constants, .tau..sub.1 =(R.sub.11S +R.sub.12S)C and .tau..sub.2 =R.sub.2S C of the loop filter 18 become small. As a result, the natural angular frequency .omega..sub.n becomes larger as is apparent from the expression (1). Accordingly, the loop bandwidth becomes wider and the frequency changeover time is made shorter.
Since the conventional frequency synthesizer is constructed as described above, the loop gain K remains unchanged and thus a great improvement in the frequency changeover time cannot be made by merely performing changes in the RC time constants used in the loop filter 18, and further difficulties are encountered upon setting of the damping coefficients to appropriate values with a mere change in the time constants, thereby causing a problem that the loop is liable to be unstable.